1. Field of the Invention
The present invention relates generally to methods for fabricating dynamic random access memory (DRAM) cell structures within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced performance, dynamic random access memory (DRAM) cell structures within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Integral to the fabrication of semiconductor integrated circuit microelectronic fabrications, and in particular to the fabrication of semiconductor integrated circuit microelectronic memory fabrications, is the fabrication of dynamic random access memory (DRAM) cell structures. As is understood by a person skilled in the art, a dynamic random access memory (DRAM) cell structure conventionally comprises a field effect transistor (FET) device in turn having formed contacting one of its source/drain regions a storage capacitor. Within the dynamic random access memory (DRAM) cell structure, a gate electrode within the field effect transistor (FET) device serves as a word line which upon actuation provides for an electrical charge introduction into the storage capacitor or an electrical charge release from the storage capacitor, while a remaining source/drain region within the field effect transistor (FET) device is contacted with a conductor layer which serves as a bit-line conductor layer for providing a conductive path for the electrical charge introduced into the storage capacitor or the electrical charge released from the storage capacitor.
A traditional requirement encountered when fabricating within semiconductor integrated circuit microelectronic fabrications dynamic random access memory (DRAM) cell structures, and in particular within the context of the inevitable conditions where semiconductor integrated circuit microelectronic fabrication device and patterned conductor layer dimensions decrease, is a need to efficiently fabricate storage capacitors with both enhanced capacitance and reduced areal dimensions, such in turn as to provide dynamic random access memory (DRAM) cell structures with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide methods and materials which may be employed to provide within semiconductor integrated circuit microelectronic fabrications dynamic random access memory (DRAM) cell structures with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the art of semiconductor integrated circuit microelectronic fabrication for fabricating, with desirable properties, dynamic random access memory (DRAM) cell structures within semiconductor integrated circuit microelectronic fabrications.
For example, Dennison, in U.S. Pat. No. 5,206,183, discloses a method for fabricating within a semiconductor integrated circuit microelectronic fabrication, and with enhanced registration alignment, a capacitor under bit-line (CUB) dynamic random access memory (DRAM) cell structure. To realize the foregoing result, the method comprises a self-aligned method which employs a plurality of process steps to form within the capacitor under bit-line (CUB) dynamic random access memory (DRAM) cell structure a storage capacitor self-aligned to a bit-line conductor contact stud layer.
In addition, Dennison et al., in U.S. Pat. No. 5,338,700, discloses an additional method for forming within a semiconductor integrated circuit microelectronic fabrication, and with enhanced storage capacitance, an additional capacitor under bit-line (CUB) dynamic random access memory (DRAM) cell structure. To realize the foregoing result, the method also comprises a self-aligned method, but the method also provides that a bit-line conductor stud layer is formed in a self-aligned fashion through an upper capacitor plate layer employed within a storage capacitor employed within the dynamic random access memory (DRAM) cell structure.
Finally, Dennison, in U.S. Pat. No. 6,083,831, discloses a method for forming within a semiconductor integrated circuit microelectronic fabrication, and upon which there may be formed a capacitor node layer with enhanced registration, a conductor contact stud layer employed within a dynamic random access memory (DRAM) cell structure. To realize the foregoing result, the method comprises a self-aligned method wherein the conductor contact stud layer is formed with a contiguous conductor collar layer surrounding its upper periphery.
Desirable in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials which may be employed for fabricating dynamic random access memory (DRAM) cell structures with enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a dynamic random access memory (DRAM) cell structure.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dynamic random access memory (DRAM) cell structure is fabricated with enhanced performance.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a dynamic random access memory (DRAM) cell structure.
To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a first source/drain region and a second source/drain region formed within the semiconductor substrate and laterally separated by a gate electrode formed upon a gate dielectric layer in turn formed upon the semiconductor substrate. There is then formed in electrical contact with the first source/drain region a capacitor node layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a capacitor plate layer in turn having formed thereupon a first mask layer, where the capacitor plate layer and the first mask layer cover the second source/drain region. There is then anisotropically etched the first mask layer and the capacitor plate layer to form a patterned first mask layer and a patterned capacitor plate layer which define a via which in turn defines in part the location of a bit-line contact layer to be formed in electrical contact with the second source/drain region. There is then isotropically etched within the via a sidewall of the patterned capacitor plate layer to form an enlarged via defined by an isotropically etched patterned capacitor plate layer recessed beneath the patterned first mask layer. There is then formed over the patterned first mask layer an inter-metal dielectric (IMD) layer which completely backfills the enlarged via. There is then formed over the inter-metal dielectric (IMD) layer a patterned second mask layer which defines an aperture which at least in part overlaps the via. Finally, there is then anisotropically etched, while employing the patterned second mask layer and the patterned first mask layer, the blanket inter-metal dielectric (IMD) layer to form a patterned inter-metal dielectric (IMD) layer which defines a bit-line via which provides electrical contact with the second source/drain region.
The present invention provides a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a dynamic random access memory (DRAM) cell structure, wherein the dynamic random access memory (DRAM) cell structure is fabricated with enhanced performance.
The present invention realizes the foregoing object with respect to a capacitor plate layer having formed thereupon a first mask layer, both of which are formed covering a second source/drain region within a field effect transistor (FET) device to which it is desired to form a bit-line contact within a dynamic random access memory (DRAM) cell structure, by providing: (1) an anisotropic etching of the first mask layer and the capacitor plate layer to form a patterned first mask layer and a patterned capacitor plate layer which define a via which in turn defines in part the location of a bit-line contact layer to be formed in electrical contact with the second source/drain region; (2) an isotropic etching within the via of a sidewall of the patterned capacitor plate layer to form an enlarged via defined by an isotropically etched patterned capacitor plate layer recessed beneath the patterned first mask layer; and (3) after forming over the patterned hard mask layer and completely backfilling the enlarged via with an inter-metal dielectric (IMD) layer in turn having formed thereover a patterned second mask layer which defines an aperture which at least in part overlaps the via, an anisotropic etching, while employing the patterned second mask layer and the patterned first mask layer, of the blanket inter-metal dielectric (IMD) layer to form a patterned inter-metal dielectric (IMD) layer which defines a bit-line via which provides electrical contact with the second source/drain region.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering to provide within the context of the present invention the method for fabricating the dynamic random access memory (DRAM) cell structure in accord with the present invention. Since it is thus at least in part a specific process ordering which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.